A conventional linear Phase-Frequency Detector (PFD) as part of a Phase-Locked Loop (PLL) and when the loop is in lock produces output pulses with narrow pulse widths, for example, pulse widths five to ten times smaller than the period of the reference signal or clock received by the conventional PFD. Further, the output pulses have a frequency equal to the frequency of the reference signal received by the conventional PFD. These narrow pulses can be difficult to generate when the PFD is dealing with high-frequency reference signals and impose a limit in the maximum frequency of the reference clock. Additionally, when the conventional PFD drives a charge-pump within a PLL and the phase difference of the inputs of the PFD is near zero, the output pulses produced by the conventional PFD, which have narrow widths and a frequency equal to the reference signal, are problematic for the associated charge-pump. That is, the narrow output signal pulse widths are difficult for the charge-pump to respond to with sufficient accuracy to produce an accurate output current representative of the phase difference detected by the conventional PFD. Further, frequency limitations of the PFD and the charge-pump impose a limit on the maximum frequency of the reference clock that can be used to run the PLL.
Operating a PLL with a reference signal of higher frequency is desirable since it lowers the division ratio of the frequency divider. That translates into a reduction of area, power, signal switching (noise) and an increase in the frequency update of the loop. That is, corrections within the loop occur more often. Consequently, the PLL produces a cleaner output signal.
As such, there exists a need for a PFD capable of operating at higher frequency rates and capable of enabling a conventional frequency-limited charge-pump to operate at such higher frequency rates. Such a PFD produces output pulses that improve the accuracy of the charge-pump and decreases its operational frequency.